1. Field of the Invention
The present invention relates to Electrically-Erasable, Programmable Read Only Memories (EEPROMs), and more particularly, but not by way of limitation, to a low-voltage EEPROM and a method for reading the same.
2. Discussion
Electrically-Erasable, Electrically Programmable Read Only Memories (EEPROMs), including Flash EEPROMs, commonly contain an array of memory cells that can be programmed and erased in-circuit. The memory cells are formed from semiconductor field effect transistors with floating gate structures. During programming, the memory cell floating gates are selectively charged to store data. To read a memory cell, a sense voltage is applied to the memory cell control gate and a read voltage is applied across the drain to source region. The drain to source current is then sensed by sense and decoding circuitry.
An important characteristic of memory cell transistors with floating gate structures is voltage threshold V.sub.t, which is the minimum voltage than can be applied to a memory cell gate (with respect to the source--V.sub.GS) to "turn on", or saturate, the memory cell and allow current to flow between the memory cell source and drain. The voltage threshold of a memory cell with an uncharged floating gate is generally much lower than the voltage threshold of that same memory cell with a charged floating gate.
The voltage thresholds of typical EEPROM memory cells in a memory array with uncharged, or erased, floating gates are not uniform, but typically range from about 1.5 V to about 3.5 V. The same EEPROM memory cells with programmed floating gates will typically have a threshold voltage range from about 5.5 V to about 7.0 V.
EEPROMs take advantage of the change in memory cell voltage threshold between erased and programmed states. During a read operation, a typical EEPROM provides a voltage V.sub.GS that is greater than the erased voltage threshold range and less than the programmed voltage threshold range; in other words between about 3.5 V and about 5.5 V. The voltage V.sub.GS is sufficient to turn on the memory cell when the floating gate is erased, but insufficient to turn on the memory cell when the floating gate is programmed. The presence of current flow from the memory cell drain to source indicates the memory cell is erased; the absence of current from drain to source indicates the memory cell is programmed.
It is important that the read voltage margin between erased and programmed voltage threshold ranges be maintained to ensure reliable read operations. If the erased and programmed voltage threshold ranges increase, the read voltage margin is decreased and the EEPROM may provide false data during read operations. EEPROM threshold voltage ranges can be difficult to control. Factors such as manufacturing variation, operating temperature, and the number of erase cycles can contribute to variations in these threshold voltage ranges.
In addition, power supply voltage can influence EEPROM read operations. Typically EEPROMs use a source voltage V.sub.cc of about 5 V, and can generally operate with power supplies providing between 4.5 V and 6 V. To read a memory cell, these EEPROMs generally apply the source voltage V.sub.cc to the memory cell gate and ground the memory cell source to achieve a V.sub.GS of about 5 V. This V.sub.GS voltage of about 5 V generally falls within the read voltage margin and allows reliable reading of memory cells in the array. Fluctuations in source voltage, however, may provide a V.sub.GS that does not fall within the read voltage margin, leading to problems during read operations.
There is an industry trend to reduce the source voltage V.sub.cc in modern electronic applications. Reducing the source voltage V.sub.cc reduces battery size and power requirements and lengthens battery life, enabling the development of smaller and longer lasting applications, especially in the areas of portable electronic devices. Modern microprocessors are presently being developed that use a source voltage V.sub.cc of 3.3 V. A source voltage of about 3 V, however, may generally not provide a sufficient gate voltage V.sub.GS to reliably read memory cells in typical EEPROMs.
One way to use a reduced source voltage of about 3 V with an EEPROM is to use conventional charge pump techniques to increase the source voltage from about 3 V to about 5 V, and apply the 5 V to the gate during a read operation. An advantage of this approach is that it allows the use of existing EEPROM memory arrays; a disadvantage of this approach, however, it that conventional charge pump techniques require a significant amount of time to increase a voltage from 3 V to 5 V. EEPROMs that use charge pump techniques to increase a source voltage V.sub.cc of about 3 V to about 5 V are generally slower, in terms of access time during read operations, than typical EEPROMs that use a source voltage V.sub.cc of about 5 V.
There are advantages to be gained if a lower source voltage V.sub.cc could be used with 5 EEPROM memory cells. One such advantage relates to reduced erased voltage threshold values and a reduction in the variation of the erased voltage threshold.
Electrically, a memory cell floating gate is a capacitor. As the charge is removed from a programmed floating gate during an erase operation, the threshold voltage on the floating gate decays in an exponential manner from an initial programmed voltage to a final erased voltage. Variations in the final erased voltage contribute to variations in the erased voltage threshold range.
FIG. 1 shows a graphical representation of the voltage threshold range of typical programmed memory cells as the memory cells are erased over time. The y-axis is memory cell voltage threshold V.sub.t and the x-axis is time. The top curve represents the maximum voltage threshold of memory cells during erasure and the bottom curve represents the minimum voltage threshold of memory cells during erasure. Thus, the area bounded by the two curves represents the voltage threshold range V.sub.t of typical memory cells during an erase operation. As can be seen, the two curves eventually converge.
At time t.sub.0, when the erase operation begins, programmed memory cells have a voltage threshold V.sub.t of from about 5.5 V to about 7.0 V.
At time t.sub.1, the voltage thresholds of the memory cells decrease to from about 1.5 V to about 3.5 V. At this point, the difference between the maximum and the minimum voltage thresholds, designated as .DELTA.1, is about 2 V. These values correspond to the typical voltage threshold range of erased memory cells. In other words, EEPROMs typically erase programmed memory cells for a duration of time about equal to the time period t.sub.1 to achieve an erased voltage threshold V.sub.t of about 1.5 V to about 3.5 V. The time period t.sub.1 is typically about 100 ms.
If memory cells continue to be erased beyond time t.sub.1, the voltage thresholds continue to decrease. A time t.sub.2, which is a time greater than t.sub.1, the voltage thresholds of the memory cells decrease from about 0 V to about 1.5 V. At this point, the difference between the maximum and the minimum voltage thresholds, designated as .DELTA.2, is about 1.5 V. Thus, at time t.sub.2, both the maximum erased voltage threshold and the variation in the erased voltage threshold range have been significantly reduced.
There are problems, however, associated with erasing memory cells for a period of time equal to t.sub.2. It may not always be feasible to erase memory cells for a time period t.sub.2, although various techniques might be employed to decrease the time period t.sub.2, such as using a higher erase voltage during the erase operation. One particularly useful method for reducing the erased voltage threshold is provided in the previously referenced U.S. patent application Ser. No. 08/349,812 entitled APPARATUS AND METHOD FOR REDUCING ERASED THRESHOLD VOLTAGE DISTRIBUTION IN FLASH MEMORY ARRAYS.
A greater problem exists, however, in reducing the minimum erased voltage threshold to a value close to, or even less than 0 V, namely, the risk of unintentionally turning on deselected memory cells during a read operation on selected memory cells in a memory array, potentially resulting in false date during the read operation. This could occur because memory cells are commonly deselected by applying 0 V (ground) to the memory cell gates. This resulting in a V.sub.GS of about 0 V, which is sufficient to turn on the deselected memory cells if the erased voltage threshold is also about 0 V.
There is a need, therefore, for a low voltage EEPROM with a conventional memory array that uses a source voltage less than 5 V, reduces power requirements, provides read access times comparable to standard 5 V EEPROMs, and reliably uses a lower erased voltage threshold.